Abstract

Memristors represent a paradigm shift in neuromorphic computing, offering non-volatile analog memory with nanoscale dimensions and ultra-low power consumption. This research investigates HfO₂-based memristor crossbar arrays for implementing hardware neural networks, achieving 100× energy efficiency improvement over traditional CMOS implementations. We demonstrate a 128×128 crossbar array capable of performing matrix-vector multiplication in a single time step, with individual devices showing excellent retention (>10⁴ s), endurance (>10⁸ cycles), and multi-level conductance states (64 levels).

Key Achievement: 91.2% accuracy on MNIST dataset with 100× lower power than GPU implementation
Background

Memristor Fundamentals: The memristor, theorized by Chua in 1971 and realized by HP Labs in 2008, is the fourth fundamental circuit element linking magnetic flux and charge.

M(q) = dφ/dq = V/I = R(q)

Key Properties:

  • Non-volatile resistance switching
  • Analog conductance modulation
  • Nanoscale dimensions (~10nm)
  • CMOS compatibility
  • Low switching energy (~1 pJ)

Switching Mechanisms:

  • Filamentary conduction (HfO₂, TaOₓ)
  • Interface switching (TiO₂/TiOₓ)
  • Phase change (GST materials)
Device Fabrication

Stack Structure:

  • Top electrode: Ti/Pt (5/50 nm)
  • Switching layer: HfO₂ (5 nm)
  • Oxygen reservoir: Ti (2 nm)
  • Bottom electrode: Pt (50 nm)
  • Substrate: SiO₂/Si

Process Flow:

  • E-beam lithography patterning
  • ALD HfO₂ deposition at 250°C
  • Reactive sputtering of electrodes
  • Junction size: 100×100 nm²
  • Forming voltage: 2.5-3.0 V
Experimental Conditions
Parameter Value
Array Size 128×128
Device Area 100×100 nm²
Ron/Roff Ratio 10²-10³
Switching Voltage ±1.5 V
Read Voltage 0.1 V
Pulse Width 100 ns
Conductance Levels 64 states
Retention >10⁴ s @ 85°C
Crossbar Architecture
Input Voltages → [Memristor Array] → Output Currents
Vi × Gij = Ij (Parallel MAC operation)

Characterization Setup:

  • Keithley 4200-SCS analyzer
  • Agilent B1500A for pulse testing
  • Custom PCB for array testing
  • LabVIEW control interface
Neural Network Mapping

Weight Mapping Scheme:

Wij = (G⁺ij - G⁻ij) × α

Where G⁺ and G⁻ represent positive and negative weights using differential encoding.

Training Algorithm:

  • Ex-situ training with TensorFlow
  • Weight quantization to 6 bits
  • Iterative write-verify programming
  • Conductance drift compensation

Network Architecture:

  • Input layer: 784 neurons (28×28)
  • Hidden layer: 128 neurons
  • Output layer: 10 neurons
  • Activation: ReLU
Results
I-V Characteristics
SET RESET
-2 -1 0 1 2 Voltage (V) 100 0 -100 I(μA)
Metric This Work CMOS
Energy/MAC 0.1 pJ 10 pJ
Area/Synapse 0.01 μm² 10 μm²
Speed 100 ns 1 ns
Retention >10⁴ s Volatile
Performance Analysis
MNIST Recognition Accuracy
SW: 98% 91.2%
0 20 40 60 80 100 Epochs 100 80 60 Acc(%)
Power Efficiency: 10 TOPS/W achieved, surpassing state-of-the-art by 2×
Device Variability
Conductance Distribution (64 levels)
σ/μ < 5%
10⁻⁸ 10⁻⁶ 10⁻⁴ Conductance (S) Count
Conclusions
  • Demonstrated 128×128 memristor crossbar with 91.2% MNIST accuracy
  • Achieved 100× energy efficiency improvement over CMOS
  • 64 distinguishable conductance levels with <5% variation
  • Retention >10⁴ s at 85°C suitable for edge AI applications
  • Scalable to larger arrays using hierarchical architecture
Future Work
  • On-chip training implementation
  • 3D vertical integration (>1M synapses)
  • Novel materials (2D TMDs, ferroelectric HfO₂)
  • Spiking neural network implementation
  • Integration with CMOS peripherals
Acknowledgments

This work was supported by NSF Grant CCF-2024789 and DARPA AI Hardware Program. The authors thank the UConn cleanroom facility for device fabrication support.