Ion Bombardment, UV Photon Damage & Charging Effects
Energetic ions penetrating the substrate create displacement damage through collision cascades. The number of Frenkel pairs (vacancy-interstitial pairs) generated is:
where Φ_ion is the ion flux (typically 10¹⁵-10¹⁷ cm⁻²s⁻¹), σ_displ is the displacement cross-section (~10⁻¹⁵ cm² for Si), and E_dep is the deposited energy per ion. At typical etch energies (100-1000 eV), each ion can create 1-10 displacement events. These defects degrade carrier mobility and increase junction leakage.
Atomic displacement occurs when transferred energy exceeds the displacement threshold energy:
The minimum ion energy for displacement is E_ion,min = 4E_d(M_ion/M_Si), where M represents atomic masses. For Ar⁺ ions on Si, this threshold is ~60 eV. Below this energy, only electronic excitation occurs without permanent lattice damage. The displacement cross-section increases sharply above threshold following the Kinchin-Pease model.
The damage layer depth is determined by ion range and straggle:
where R_p is the projected range (mean penetration depth) and ΔR_p is the range straggle (standard deviation). For 500 eV Ar⁺ in Si, R_p ≈ 2.5 nm and ΔR_p ≈ 1.2 nm. The damage profile follows a Gaussian-like distribution with peak defect density at depth R_p. Higher energy ions penetrate deeper, potentially damaging buried oxide layers or channel regions in MOSFETs.
Plasma-generated UV photons (λ < 200 nm) are absorbed in dielectrics, creating bond-breaking damage:
UV photons with energy > 6 eV can break Si-O bonds (bond energy ~8 eV through multiphoton absorption), creating E' centers (≡Si•) and non-bridging oxygen hole centers (≡Si-O•). These defects act as charge traps, shifting threshold voltage and degrading oxide reliability. The damage rate scales with UV flux, which can exceed 10¹⁶ photons/cm²/s in high-density plasmas.
In high aspect ratio features, electron and ion currents become imbalanced:
Electrons have higher mobility and are shadowed by trench walls, while ions have directional trajectories. This creates positive charging at trench bottoms. The charging voltage builds up as V_charge = ∫(ΔI/C)dt, where C is the local capacitance. Voltages can exceed 50-100V, causing gate oxide breakdown or threshold voltage shifts in transistors.
Charging-induced notching at the trench bottom follows:
where k is a material-dependent constant (~0.1 nm/V^1.5/s^0.5), V_charge is the charging voltage, and t is exposure time. The 1.5 power dependence comes from ion deflection angle scaling with voltage. Notching is particularly severe in oxide-over-silicon etching where the oxide acts as a charging dielectric. Notch depths of 10-50 nm are common in high-AR features, causing device shorts.
Surface damage creates stochastic line edge roughness:
where PSD(f) is the power spectral density measured by AFM or top-down SEM. Ion bombardment damage creates surface roughness through micro-masking by redeposition, differential sputtering of damaged regions, and stochastic ion impact. LER scales with √(ion dose) and increases with ion energy. For sub-7nm nodes, LER must be < 2 nm to avoid device performance variation.
Thermal annealing can partially recover damage through defect recombination:
where N is defect density, τ_anneal is the attempt frequency (~10⁻¹³ s), E_a is activation energy (0.5-2.5 eV for different defect types in Si), k is Boltzmann constant, and T is temperature. At 400°C, simple interstitials anneal in minutes, but complex defect clusters require > 800°C. Some UV-induced oxide defects are permanent and cannot be annealed below 1000°C.
The number of stable displacements per ion follows the Kinchin-Pease relationship:
where E_damage is the energy available for atomic displacements (total ion energy minus electronic losses) and E_d is the displacement energy. The factor 0.8 accounts for recombination of close Frenkel pairs. For 500 eV Ar⁺ in Si, with 70% energy going to nuclear collisions, N_d ≈ 10-15 displacements per ion. In reality, cascade overlap and channeling effects modify this prediction.
In high aspect ratio trenches, electron flux to the bottom is reduced:
where AR is aspect ratio, λ_e is electron mean free path (~1-2 mm at typical pressures), and Γ represents flux. For AR = 10, bottom electron flux is reduced by 100-1000×, while ion flux (mean free path ~cm) is unaffected. This explains the quadratic increase of charging voltage with aspect ratio observed experimentally.
UV photons and energetic electrons create paramagnetic E' centers:
E' centers are the dominant hole trap in SiO₂, with trap energy ~5.8 eV below conduction band. Densities can reach 10¹²-10¹³ cm⁻² in gate oxides after plasma exposure, causing 10-100 mV threshold voltage shifts. These defects are particularly damaging for thin gate oxides (< 3 nm) where trap densities > 10¹¹ cm⁻² cause unacceptable device variation.
Antenna ratio (ratio of metal area to gate oxide area) must be limited to < 100-500 to avoid breakdown. Plasma-induced damage can reduce breakdown field by 30-50% compared to virgin oxides, requiring more conservative antenna design rules.
Ion bombardment creates interface states at Si/SiO₂ boundaries:
where D_it,0 is the initial interface state density (~10¹⁰ cm⁻²eV⁻¹ for good quality oxide), k_damage is damage coefficient (~10⁻⁷ cm²), and f(E_ion) scales as E_ion^1.5 above threshold. Interface states degrade subthreshold swing (60 + kT/q × ln(10) × (C_it/C_ox) mV/dec) and increase OFF-state leakage. Damage can increase D_it by 10-100× in worst case.