3-Stage SST Architecture

System Overview

The proposed solid-state transformer architecture employs a modular 3-stage topology designed for bidirectional power flow, high efficiency, and grid service capability. Each stage is optimized for specific voltage levels and functionality, leveraging wide-bandgap semiconductors to achieve high power density and efficiency.

Key Design Principles:
  • Modular architecture for scalability and redundancy
  • Galvanic isolation via medium-frequency transformer
  • Wide-bandgap devices for high-frequency operation
  • Integrated fault tolerance and protection

Stage 1: Three-Level NPC Rectifier

Topology Analysis

The neutral-point-clamped (NPC) rectifier provides AC-DC conversion with reduced voltage stress on semiconductors, lower harmonic distortion, and improved efficiency compared to two-level topologies. The three-level structure enables direct connection to medium voltage grids without series connection of devices.

DC Link Voltage:
\[ V_{dc} = \sqrt{2} \cdot V_{LL} \cdot m_a \] where \( m_a \) is the modulation index (typically 0.9-0.95)

Component Selection

Component Specification Selected Device Rationale
Main Switches 3.3 kV, 450 A Wolfspeed CAB450M12XM3 Low Rds_on, high temp operation
Clamping Diodes 3.3 kV, 300 A SiC Schottky Diodes Zero reverse recovery
DC Link Capacitor 20 kV, 5 mF Film Capacitor Bank Low ESR, high ripple current
Input Filter LCL Configuration L1=2mH, C=50μF, L2=1mH THD < 3%, resonance damping

Interactive Design Tool

13.8 kV
5.0 kHz
19.5
DC Link (kV)
2.8
THD (%)
98.2
Efficiency (%)

Stage 2: Dual Active Bridge with MF Transformer

DAB Operation Principle

The dual active bridge provides bidirectional power transfer with galvanic isolation through a medium-frequency transformer. Power flow is controlled via phase-shift modulation between primary and secondary bridges, enabling soft-switching operation across a wide load range.

Power Transfer Equation:
\[ P = \frac{n \cdot V_1 \cdot V_2}{2\pi f_s L_{lk}} \cdot \phi \left(1 - \frac{|\phi|}{\pi}\right) \] where \( \phi \) is the phase shift, \( L_{lk} \) is leakage inductance

MF Transformer Design

Core Selection

  • • Material: Nanocrystalline (Vitroperm 500F)
  • • Core Type: C-Core Configuration
  • • Effective Area: 45 cm²
  • • Window Area: 120 cm²
  • • Operating Flux: 0.8 T @ 50 kHz

Winding Design

  • • Primary: 28 turns, Litz wire 1000×0.2mm
  • • Secondary: 3 turns, copper foil 0.5mm
  • • Turns Ratio: 9.33:1
  • • Leakage Inductance: 25 μH (designed)
  • • Insulation: Nomex, 50 kV BIL

Stage 3: LV Output Converter

Configuration Options

DC Output (DCFC Mode)

Regulated DC bus for EV fast charging

  • • Output: 400-1000 VDC adjustable
  • • Current: up to 500 A
  • • Ripple: < 1% peak-to-peak
  • • Protocol: CCS/ChaoJi compatible

AC Output (Grid-Tie Mode)

Three-phase inverter for grid connection

  • • Output: 480 VAC, 3-phase
  • • THD: < 3% at rated load
  • • Power Factor: 0.8 leading to lagging
  • • Grid Services: Volt-VAR, frequency support

GaN Device Implementation

The LV stage utilizes GaN HEMTs for high-frequency operation with minimal switching losses. The enhanced electron mobility and low gate charge enable switching frequencies up to 200 kHz, reducing passive component size and improving dynamic response.

Parameter GaN HEMT Si MOSFET Improvement
Switching Frequency 200 kHz 50 kHz
Switching Loss 0.2 mJ 0.8 mJ 75% reduction
Power Density 8 kW/L 3 kW/L 2.7×

System Integration & Control

Hierarchical Control Architecture

Level 1 - Device Control (FPGA): PWM generation, dead-time insertion, protection

Level 2 - Converter Control (DSP): Current/voltage loops, phase-shift control, MPPT

Level 3 - System Control (ARM): Power management, grid services, communication

Protection & Fault Management

Critical Protection Features:
  • Overcurrent protection with di/dt detection
  • Overvoltage clamping and crowbar circuits
  • Thermal monitoring with predictive derating
  • Ground fault detection and isolation
  • Arc flash mitigation systems

Experimental Validation

Prototype Specifications

Parameter Design Target Measured Value Status
Power Rating 350 kW 352 kW ✓ Achieved
Peak Efficiency 98.5% 98.3% ✓ Close
Power Density 5 kW/L 4.8 kW/L ○ Optimizing
Input THD < 3% 2.4% ✓ Achieved
ZVS Range 20-100% 25-100% ✓ Achieved