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Vertical GaN Power Electronics

Comprehensive Technical Documentation

Table of Contents

1 Introduction

Vertical gallium nitride (GaN) power devices represent a paradigm shift in high-voltage power electronics. By leveraging the superior material properties of GaN in a vertical architecture, these devices overcome the fundamental limitations of lateral GaN structures while achieving performance metrics that surpass silicon carbide (SiC) in many applications.

1.1 Historical Context

The development of vertical GaN technology emerged from the need to extend GaN's exceptional performance into the >1kV domain. While lateral GaN-on-Si devices revolutionized sub-650V applications, voltage scaling limitations and thermal constraints prevented their adoption in higher voltage systems.

1.2 Technology Overview

Vertical GaN devices conduct current perpendicular to the wafer surface through a thick drift region, similar to traditional silicon and SiC power devices. This architecture provides several key advantages:

  • Voltage scaling with drift layer thickness
  • Superior thermal dissipation through the substrate
  • Elimination of surface field crowding
  • Higher current density capability
  • Avalanche robustness

2 GaN Material Fundamentals

2.1 Crystal Structure and Properties

GaN crystallizes in the wurtzite structure with strong ionic character in its covalent bonds. This unique bonding arrangement results in spontaneous and piezoelectric polarization effects that are fundamental to device operation.

Property GaN SiC (4H) Si Unit
Bandgap (Eg) 3.4 3.3 1.1 eV
Critical Field (Ec) 3.3 2.5 0.3 MV/cm
Electron Mobility (μn) 1500 1000 1400 cm²/V·s
Saturation Velocity (vsat) 2.5 2.0 1.0 ×10⁷ cm/s
Thermal Conductivity (κ) 2.3 3.7 1.5 W/cm·K

2.2 Polarization Effects

The wurtzite crystal structure lacks inversion symmetry, leading to spontaneous polarization along the c-axis. Additionally, strain in heterostructures induces piezoelectric polarization:

Total Polarization
\[ P_{total} = P_{sp} + P_{pz} = P_{sp} + 2 \frac{a - a_0}{a_0} \left( e_{31} - e_{33} \frac{C_{13}}{C_{33}} \right) \]

2.3 Two-Dimensional Electron Gas (2-DEG)

At the AlGaN/GaN heterojunction, polarization discontinuity creates a sheet charge density that induces the formation of a 2-DEG:

2-DEG Sheet Charge Density
\[ n_s = \frac{\sigma_{pol}}{q} - \frac{\epsilon_0 \epsilon_r}{q^2 d} (q\phi_b + E_F - \Delta E_c) \]

3 Vertical Device Physics

3.1 Device Structure

The basic vertical GaN power device consists of:

  • N+ GaN substrate: Low-resistance current path and heat sink
  • N- GaN drift layer: Voltage blocking region
  • P-type base/body: Channel formation region
  • N+ source: Electron injection
  • Gate structure: Channel control (MOS or junction gate)

3.2 Current Conduction Mechanisms

Current flow in vertical GaN devices involves multiple mechanisms:

3.2.1 Channel Conduction

Channel Current (Linear Region)
\[ I_{DS} = \frac{W}{L} \mu_n C_{ox} \left[ (V_{GS} - V_{th})V_{DS} - \frac{V_{DS}^2}{2} \right] \]

3.2.2 Drift Region Conduction

Drift Resistance
\[ R_{drift} = \frac{4 V_{BR}^2}{\epsilon_s \mu_n E_c^3 A} \]

3.3 Breakdown Mechanisms

Vertical GaN devices exhibit avalanche breakdown behavior, providing inherent robustness against voltage transients:

Impact Ionization Coefficient
\[ \alpha_n = a_n \exp\left(-\frac{b_n}{E}\right) \]

where an = 2.9 × 10⁸ cm⁻¹ and bn = 3.4 × 10⁷ V/cm for GaN

4 Fabrication Technology

4.1 Substrate Technology

The availability of high-quality, low-defect GaN substrates is crucial for vertical device fabrication. Several approaches are employed:

Method Defect Density Diameter Cost Status
HVPE Bulk GaN 10⁴-10⁶ cm⁻² 2-4 inch High Commercial
Ammonothermal 10³-10⁴ cm⁻² 2 inch Very High Limited
Na-flux 10²-10³ cm⁻² 2 inch Very High R&D
GaN-on-GaN Template 10⁶-10⁷ cm⁻² 4-6 inch Medium Emerging

4.2 Epitaxial Growth

Metal-organic chemical vapor deposition (MOCVD) is the primary technique for growing device structures: 

# MOCVD Growth Sequence for Vertical GaN FET

1. Substrate preparation and in-situ cleaning
   - H₂ bake at 1050°C for 10 min
   
2. N+ buffer layer (Si: 5×10¹⁸ cm⁻³)
   - Temperature: 1050°C
   - V/III ratio: 2000
   - Growth rate: 2 μm/hr
   
3. N- drift layer (Si: 1×10¹⁶ cm⁻³)
   - Temperature: 1050°C
   - V/III ratio: 3000
   - Thickness: 10-20 μm for 1.2-3kV
   
4. P-type base (Mg: 1×10¹⁸ cm⁻³)
   - Temperature: 950°C
   - Cp₂Mg flow rate calibration critical
   
5. N+ source regions (selective regrowth)
   - Si: 1×10¹⁹ cm⁻³

4.3 Process Integration Challenges

  • P-type doping: Mg activation and memory effects
  • Selective area regrowth: Interface quality control
  • Edge termination: Multi-zone JTE or guard rings
  • Gate dielectric: Interface state density minimization
  • Ohmic contacts: Low-resistance n-type and p-type contacts

5 Device Design Considerations

5.1 Drift Layer Design

The drift layer design involves optimizing thickness and doping for the target breakdown voltage while minimizing on-resistance:

Optimal Drift Layer Doping
\[ N_D^{opt} = \frac{\epsilon_s E_c^2}{2 q V_{BR}} \]
Minimum Drift Layer Thickness
\[ W_{drift}^{min} = \frac{2 V_{BR}}{E_c} \]

5.2 Edge Termination Design

Proper edge termination is critical for achieving theoretical breakdown voltage:

Edge Termination Techniques
  • Junction Termination Extension (JTE): Graded p-type implantation
  • Guard Rings: Multiple floating p-type rings
  • Field Plates: Metal field spreading structures
  • Bevel Edge: Angled mesa for field distribution

5.3 Gate Structure Options

5.3.1 Trench MOSFET

  • Vertical channel along trench sidewall
  • High channel density
  • Gate oxide reliability challenges

5.3.2 Current Aperture Vertical Electron Transistor (CAVET)

  • Combines lateral 2-DEG channel with vertical drift
  • Lower channel resistance
  • Complex fabrication

5.3.3 Junction FET (JFET)

  • P-type gate regions
  • Normally-on operation
  • Robust and simple structure

6 Performance Characteristics

6.1 Static Characteristics

Parameter 1.2kV Vertical GaN 1.2kV SiC MOSFET 650V Lateral GaN
Specific On-Resistance 0.8-1.0 mΩ·cm² 2.5-3.5 mΩ·cm² 1.0-1.5 mΩ·cm²
Threshold Voltage 2-3 V 2-4 V 1-2 V
Max Junction Temp 175°C 175°C 150°C
Avalanche Capability Yes Yes Limited

6.2 Dynamic Characteristics

6.2.1 Switching Performance

Turn-on Time
\[ t_{on} = t_{d(on)} + t_r = R_G C_{iss} \ln\left(\frac{V_{DD}}{V_{DD} - V_{th}}\right) + \frac{Q_{gd}}{I_G} \]

6.2.2 Switching Loss Analysis

Loss Component Expression Vertical GaN Advantage
Turn-on Loss Eon = ½VDSIDtr 3-5× lower tr
Turn-off Loss Eoff = ½VDSIDtf 3-5× lower tf
Output Capacitance Eoss = ½CossVDS² 2-3× lower Coss

6.3 Reliability Considerations

Key Reliability Metrics
  • HTRB (High Temperature Reverse Bias): >1000 hrs at 175°C, 80% Vrated
  • HTGB (High Temperature Gate Bias): >1000 hrs at 175°C, VGS,max
  • Dynamic RDS(on): <10% increase after switching stress
  • Cosmic Ray Robustness: >80% of breakdown voltage

7 Applications & Circuit Design

7.1 Target Applications

Application Voltage Range Power Level Key Benefits
EV Traction Inverters 400-800V 50-300kW Size reduction, efficiency
DC Fast Chargers 400-1000V 50-350kW Power density, cost
Solar Inverters 1000-1500V 100kW-1MW Efficiency, reliability
Data Center Power 400-800V 10-100kW Efficiency at light load
Grid Tie Converters 1000-3000V >1MW Lower part count

7.2 Circuit Design Guidelines

7.2.1 Gate Drive Requirements

# Recommended Gate Drive Parameters

V_GS(on) = +15V to +18V     # Full enhancement
V_GS(off) = -3V to -5V      # Fast turn-off, prevent false turn-on
R_G(on) = 2-5 Ω             # Control dv/dt and di/dt
R_G(off) = 1-2 Ω            # Fast turn-off
Gate drive power > 1W       # High-frequency operation

7.2.2 Layout Considerations

  • Minimize power loop inductance: <5nH target
  • Kelvin source connection: Separate power and gate return
  • Thermal management: Direct substrate cooling preferred
  • EMI mitigation: Controlled dv/dt with gate resistance

7.3 System-Level Benefits

System Power Density Improvement
\[ \frac{P_{density,GaN}}{P_{density,Si}} = \frac{f_{sw,GaN}}{f_{sw,Si}} \times \frac{\eta_{GaN}}{\eta_{Si}} \approx 3-5× \]

8 Future Developments

8.1 Technology Roadmap

Timeframe Voltage Class Ron,sp Key Milestones
2024-2025 1.2kV <1 mΩ·cm² Commercial introduction
2025-2027 1.7kV <2 mΩ·cm² 4-inch substrate adoption
2027-2030 3.3kV <5 mΩ·cm² Grid-scale deployment
Beyond 2030 >6kV <10 mΩ·cm² HVDC applications

8.2 Research Directions

8.2.1 Material Improvements

  • Ultra-low defect density substrates (<10³ cm⁻²)
  • P-type doping enhancement (hole concentration >10¹⁹ cm⁻³)
  • Novel heterostructures (InGaN, AlInGaN)

8.2.2 Device Innovations

  • Super-junction structures for ultra-low Ron
  • Integrated gate drivers and protection
  • Multi-level devices for >6kV operation

8.2.3 Manufacturing Advances

  • 6-inch and 8-inch GaN substrate development
  • Cost reduction through economies of scale
  • Foundry-compatible process flows

9 References

[1] Y. Zhang et al., "Vertical GaN Junction Field-Effect Transistors with Avalanche Capability," IEEE Electron Device Letters, vol. 40, no. 1, pp. 75-78, 2019.
[2] T. Oka, "Recent development of vertical GaN power devices," Japanese Journal of Applied Physics, vol. 58, no. SB, p. SB0805, 2019.
[3] R. J. Kaplar et al., "Review—Ultra-Wide-Bandgap AlGaN Power Electronic Devices," ECS Journal of Solid State Science and Technology, vol. 6, no. 2, p. Q3061, 2017.
[4] H. Nie et al., "1.5-kV and 2.2-mΩ·cm² Vertical GaN Transistors on Bulk-GaN Substrates," IEEE Electron Device Letters, vol. 35, no. 9, pp. 939-941, 2014.
[5] D. Shibata et al., "1.7 kV/1.0 mΩ·cm² normally-off vertical GaN transistor on GaN substrate," IEEE International Electron Devices Meeting (IEDM), pp. 10.1.1-10.1.4, 2016.
[6] I. C. Kizilyalli et al., "Vertical Power p-n Diodes Based on Bulk GaN," IEEE Transactions on Electron Devices, vol. 62, no. 2, pp. 414-422, 2015.
[7] M. Sun et al., "High-Performance GaN Vertical Fin Power Transistors on Bulk GaN Substrates," IEEE Electron Device Letters, vol. 38, no. 4, pp. 509-512, 2017.
[8] S. Chowdhury et al., "CAVET on Bulk GaN Substrates Achieved With MBE-Regrown AlGaN/GaN Layers," IEEE Electron Device Letters, vol. 33, no. 1, pp. 41-43, 2012.

Additional Resources

Technical Standards

  • JEDEC JEP180: Guidelines for GaN Power Conversion Devices
  • AEC-Q101: Automotive Grade Discrete Semiconductors
  • IEC 60747-8: Discrete semiconductor devices - Field-effect transistors

Industry Organizations

  • Power Electronics Industry Collaborative (PEIC)
  • JEDEC JC-70 Wide Bandgap Committee
  • IEEE Power Electronics Society (PELS)

Simulation Tools

  • Synopsys Sentaurus TCAD for device simulation
  • Silvaco Atlas for GaN device modeling
  • ANSYS Q3D for parasitic extraction
  • LTspice/PLECS for circuit simulation