The Partitioned Memristor Neural Accelerator (PMNA) represents a paradigm shift in AI hardware acceleration. By leveraging the unique properties of memristor devices arranged in crossbar arrays, we can perform neural network computations directly in the analog domain, achieving unprecedented energy efficiency and speed.
Eliminates data movement between memory and processing units by computing directly where data is stored.
Exploits Ohm's law and Kirchhoff's current law for natural matrix-vector multiplication.
Thousands of multiply-accumulate operations happen simultaneously in a single time step.
Each memristor in the crossbar array represents a synaptic weight in the neural network. The conductance (G = 1/R) of the memristor encodes the weight value.
The fundamental operation in neural networks is vector-matrix multiplication. In our memristor crossbar:
Where:
To overcome the limitations of large monolithic crossbars, we implement a partitioned architecture:
Digital inputs are converted to analog voltages via DACs and distributed to multiple crossbar partitions.
Each partition performs VMM independently, computing a portion of the overall matrix multiplication.
Output currents from each column are summed according to Kirchhoff's current law.
Summed currents are converted back to digital values via ADCs for further processing or output.
# Neural network weight matrix
W = [[0.5, -0.3, 0.8],
[0.2, 0.7, -0.4],
[-0.6, 0.1, 0.9]]
# Map to conductance values
G_positive = max(0, W) / R_on
G_negative = max(0, -W) / R_on
# Program memristors
for i, j in crossbar:
memristor[i,j].set_conductance(G_positive[i,j])
memristor[i,j+offset].set_conductance(G_negative[i,j])
For higher precision, we use multiple memristors per weight:
| Aspect | GPU/CPU | PMNA | Improvement |
|---|---|---|---|
| Energy per MAC | ~1-10 pJ | ~0.1 pJ | 10-100× |
| Memory Bandwidth | Limited by bus | In-memory | ∞ |
| Parallelism | ~1000s ops | ~1M ops | 1000× |
| Area Efficiency | Large | Compact | 100× |
Challenge: Voltage degradation along wires in large arrays.
Solution: Partitioned architecture reduces array size, minimizing IR drop effects.
Challenge: Manufacturing variations in memristor properties.
Solution: Variation-aware training and calibration algorithms.
Challenge: Analog computation has inherent noise.
Solution: Multi-bit representation and error correction techniques.
Measures computational throughput. Our design achieves 1000 TOPS peak performance.
Energy efficiency metric. We achieve 20 TOPS/W, 200× better than GPUs.
Time for one inference. Analog computation provides <1μs latency.
The field of memristor-based neural accelerators is rapidly evolving. Future developments include: