Neural Network Accelerator on Partitioned Memristor Crossbar

Configuration

Network Architecture

Input Size:

Hidden Layer 1:

Hidden Layer 2:

Output Size:

Crossbar Configuration

Crossbar Size:

Partitioning:

Weight Bits:

ADC Resolution:

Device Parameters

R_on (kΩ):

R_off (MΩ):

Variation (%):

Network Mapping Visualization

0

Total Crossbars Required

0%

Crossbar Utilization

0 pJ

Energy per Operation

0 TOPS

Theoretical Throughput