Research Papers in Progress

Current Research Portfolio

6
Papers in Progress
4
Target Conferences
2
Journal Submissions
3
Collaborative Projects
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Partitioned Memristor Crossbar Architecture for Energy-Efficient Neural Network Acceleration Target: Best Paper
L. Antoine, [Collaborator 1], [Collaborator 2], [Collaborator 3]
Target: IEEE International Symposium on Circuits and Systems (ISCAS) 2025
We present a novel partitioned crossbar architecture that mitigates IR drop effects in large-scale memristor arrays. Our approach divides a 256×256 crossbar into 128×128 sub-arrays, achieving 45% reduction in maximum voltage drop and 3.2× improvement in computation accuracy. Experimental results on fabricated HfO₂-based devices demonstrate 20 TOPS/W energy efficiency for neural network inference.
Crossbar Architecture IR Drop Mitigation Hardware Implementation
Comprehensive Modeling of HfO₂-based Memristors: From Physics to System-Level Simulation
L. Antoine, [Collaborator 1], [Collaborator 2], [Collaborator 3]
Target: Nature Electronics (In Preparation)
This work presents a multi-scale modeling framework for HfO₂-based memristors, bridging atomistic simulations with system-level performance. We develop a compact model that captures switching dynamics, variability, and reliability metrics. The model is validated against experimental data from over 10,000 devices, showing excellent agreement across six orders of magnitude in timescale.
Device Physics Compact Modeling Variability Analysis
Variation-Aware Training for Memristor-Based Neural Networks
L. Antoine, [Collaborator 1], [Collaborator 2], [Collaborator 3]
Target: International Conference on Machine Learning (ICML) 2025
We introduce a novel training methodology that accounts for device-to-device and cycle-to-cycle variations in memristor crossbars. Our approach uses stochastic gradient descent with hardware-aware noise injection, achieving 96.2% accuracy on CIFAR-10 despite 15% device variation. The method reduces accuracy degradation by 8.5× compared to conventional training.
Machine Learning Robust Training Hardware-Software Co-design
Real-Time Object Detection on Memristor Crossbars: A 1000 FPS Implementation
L. Antoine, [Collaborator 1], [Collaborator 2], [Collaborator 3]
Target: IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) 2025
We demonstrate real-time object detection running entirely on memristor crossbar arrays, achieving 1000+ FPS on 640×480 images with 82.3% mAP on COCO dataset. The implementation uses a custom YOLO-variant optimized for analog computing, consuming only 2.5W total power.
Computer Vision Edge AI Real-time Processing
3D Integration of Memristor Crossbars: Design, Fabrication, and Characterization
L. Antoine, [Collaborator 1], [Collaborator 2], [Collaborator 3]
Target: IEEE Transactions on Electron Devices (Under Review)
This paper presents the first demonstration of 3D-stacked memristor crossbar arrays with 8 active layers. We develop novel via technology for inter-layer connectivity and thermal management solutions. The 3D architecture achieves 12.5 Gb/cm² density while maintaining switching characteristics comparable to 2D arrays.
3D Integration Fabrication Thermal Management
Multi-Level Cell Programming in HfO₂ Memristors for Increased Storage Density
L. Antoine, [Collaborator 1], [Collaborator 2]
Target: IEEE International Memory Workshop (IMW) 2025
We demonstrate reliable 4-bit (16-level) programming in HfO₂-based memristors using optimized pulse sequences. Our approach achieves 2% cell-to-cell variation and >10⁵ endurance cycles. The multi-level capability increases effective storage density by 4× without area overhead.
Multi-level Cell Programming Algorithms Reliability

Research Progress Timeline

Target Venues & Submission Timeline