Design Examples

Real-world RF and SiP design examples

5G mmWave Module

28 GHz AiP with 8×8 phased array

Complete antenna-in-package design for 5G NR FR2. Includes patch array, beamforming IC interface, and thermal management.

28 GHz 8×8 Array ±60° Steering 
# mmWave AiP Design
from rf_design.antenna import PatchAntenna, PhasedArray

# Design patch element
patch = PatchAntenna(
    freq=28e9,
    er=3.0,
    height=0.127e-3
)

# Create 8x8 array
array = PhasedArray(
    element=patch,
    nx=8, ny=8,
    dx=0.5, dy=0.5  # wavelengths
)

# Apply Taylor taper for -25 dB SLL
array.set_taper('taylor', sll=-25)

# Calculate gain
print(f"Array gain: {array.gain():.1f} dBi")
FCBGA Package

112G SerDes Channel

PAM4 high-speed interface design

High-speed SerDes channel from die through package to PCB. Includes bump-out, via transitions, and differential routing.

112 Gbps PAM4 BER < 1e-12 
# SerDes Channel Analysis
from rf_design.si import Channel, Equalizer

# Load channel S-parameters
channel = Channel.from_file("serdes_channel.s4p")

# Configure PAM4 signaling
channel.set_signaling('pam4', baud=56e9)

# Optimize equalization
eq = Equalizer(tx_ffe=3, rx_ctle=True, rx_dfe=10)
eq.optimize(channel, target_ber=1e-12)

# Generate eye diagram
eye = channel.simulate_eye(eq, bits=1e6)
print(f"Eye height: {eye.height:.3f} V")
print(f"Eye width: {eye.width:.2f} UI")
12L Substrate

WiFi 7 FEM

Front-end module with integrated PA/LNA

WiFi 7 front-end module supporting 2.4/5/6 GHz bands. Includes matching networks, filters, and antenna switch.

Tri-band 320 MHz BW +23 dBm 
# WiFi FEM Design
from rf_design import LMatch, BandPassFilter

# 5 GHz band matching network
match_5g = LMatch(
    zs=50+0j,
    zl=15+20j,  # PA output impedance
    freq=5.5e9
)

# SAW filter for 6 GHz band
filter_6g = BandPassFilter(
    fc=6.25e9,
    bw=500e6,
    order=5,
    type='chebyshev'
)

print(f"Match: L={match_5g.L*1e9:.2f}nH, C={match_5g.C*1e12:.2f}pF")
QFN 4×4mm

DDR5 Interface

High-speed memory channel design

DDR5-6400 memory interface from SoC to DRAM. Includes length matching, termination, and power integrity co-design.

6400 MT/s x64 1.1V VDDQ 
# DDR5 SI Analysis
from rf_design.si import DDR5Channel

# Create DDR5 channel model
ddr = DDR5Channel(
    data_rate=6400e6,   # MT/s
    vddq=1.1,
    z0=40               # Target impedance
)

# Analyze eye at DRAM receiver
eye = ddr.analyze_eye(
    length=50e-3,       # 50mm trace
    vias=4,
    connectors=0
)

# Check timing margins
print(f"Setup margin: {ddr.setup_margin():.0f} ps")
print(f"Hold margin: {ddr.hold_margin():.0f} ps")
POD termination

77 GHz Automotive Radar

FMCW radar transceiver module

77 GHz automotive radar module with integrated TX/RX chains, antenna array, and thermal management for ADAS applications.

77 GHz FMCW AEC-Q100 
# Automotive Radar Design
from rf_design.radar import FMCWRadar

radar = FMCWRadar(
    freq=77e9,
    bandwidth=4e9,      # 4 GHz sweep
    chirp_time=40e-6    # 40 µs chirp
)

# Calculate range resolution
range_res = radar.range_resolution()
print(f"Range resolution: {range_res*100:.1f} cm")

# Design TX antenna array
tx_array = radar.design_tx_array(
    gain=12,            # dBi target
    azimuth_bw=30       # degrees
)
-40 to +125°C

2.5D MCM

Multi-chip module with interposer

2.5D multi-chip module with silicon interposer connecting compute die to HBM3. High-bandwidth, low-latency interconnect.

2.5D Si HBM3 1 TB/s 
# 2.5D MCM Design
from rf_design.mcm import Interposer, Die

# Create silicon interposer
interposer = Interposer(
    size=(25e-3, 35e-3),  # 25x35mm
    thickness=100e-6,      # 100µm
    rdl_layers=4
)

# Add compute die
compute = Die("compute", size=(10e-3, 10e-3))
interposer.place(compute, x=5e-3, y=12e-3)

# Add HBM stacks
for i in range(4):
    hbm = Die(f"hbm{i}", size=(5e-3, 8e-3))
    interposer.place(hbm, x=18e-3, y=2e-3 + i*9e-3)
µ-bumps