RF/High-Speed SiP Co-Design

Advanced System-in-Package platform integrating phased-array RF front-ends and high-speed chiplet interconnects with full-wave EM co-simulation

28 GHz mmWave 5G NR 112 Gbps SerDes EM Co-Simulation
28 GHz
Operating Frequency
-25 dB
Return Loss (S11)
112 Gbps
Data Rate
4×4
Antenna Array

Project Overview

Developed a comprehensive 3D heterogeneous integration solution for RF front-end modules targeting 5G mmWave applications and high-speed chiplet interconnects. This project demonstrates advanced co-design methodologies combining electromagnetic simulation, thermal analysis, and signal integrity optimization.

Key innovations include novel antenna-in-package (AiP) design, compartmental EM shielding, and multi-physics co-optimization for next-generation System-in-Package (SiP) technologies.

Key Features

  • 28 GHz phased array antenna-in-package (4×4)
  • 112 Gbps PAM4 SerDes signal integrity
  • 3D EM co-simulation with HFSS/ADS
  • Thermal-aware power distribution network
  • UCIe chiplet interconnect design

Interactive Demos

Design Tools

Documentation

System Architecture

RF Front-End Module

  • 28 GHz phased array antenna (4×4)
  • GaN PA with 20 dBm output power
  • LNA with 2.5 dB noise figure
  • Integrated T/R switch and phase shifters

Packaging Technology

  • Fan-out wafer level packaging (FOWLP)
  • Through-silicon vias (TSV) integration
  • Embedded die technology
  • Low-loss organic substrate (Df < 0.003)

Key Results

  • < -10 dB return loss across 26-30 GHz band
  • Antenna gain of 12 dBi with ±45° beam steering
  • RF-digital crosstalk < -40 dB
  • Thermal resistance 2.5 °C/W with heat spreader
  • 64-QAM modulation at 2 Gsps demonstrated

Tools & Technologies

Ansys HFSS CST Studio Suite Keysight ADS Ansys Icepak Ansys SIwave Cadence Allegro MATLAB Python